A partner integrates the local path into its own hardware; scope and licensing follow the actual integration.
OSH GLOBAL SYSTEMS, INC. APPLIED RESEARCH / 2026
A newcomputationalorganism.
OSH is a homeostatic semantic organism: an architecture that preserves internal state, changes as events unfold, and can choose an action locally. It first ran on a PC. Its causal path was then executed on physical ESP32-S3 hardware.
01 / PCResident runtimeBenchmark 3 · video and measurements
02 / ESP32-S3Physical siliconCausal parity and a closed loop
03 / PORTABILITYFour familiesCross-compilation; physical testing pending
00 / WHAT IS OSH
What is OSH, and how does it work?
In plain terms, OSH maintains an internal state shaped by experience and its environment. When a signal arrives, it adjusts that state, evaluates possible paths, and selects what to do. The process can continue from one cycle to the next.
PERSISTENCEState and continuity persist across cycles.
REGULATIONInternal conditions guide trajectory, attention, and selection.
EXPRESSIONText and speech are downstream outputs; they do not govern the tested cognitive path.
LOCAL EXECUTIONThe validated core can act on an ESP32-S3 without cloud inference.
01 / BENCHMARK 3 FIRST ON A PC
INTEL ATOM D2500 · CPU ONLY · 12 SEP 2026B3 01 / PC STAGE
Benchmark 3.
OSH on a PC.
Before moving to a microcontroller, OSH ran on a PC. The recording shows José Fabián typing in the real OSH interface. The separate report measures the resident runtime on an Intel Atom D2500 under a 30-input protocol.
REAL SCREEN / OSH ON PCDEMO.MP4 · 00:46
The recording shows the conversation and the OSH / STRUCTURAL TELEMETRY panel. It documents the interface in use; the reproducible measurements are in the report.
Open demo.mp4 ↗The player could not load the video. Watch the video from the repository ↗
PROTOCOL / 30 INPUTSGPU = 0
OSH MEDIAN6.466 ms
Structured resident runtime cycle.
TINYLLAMA 1.1B · ONE TOKEN18,186.463 ms
MEDIAN RUNTIME RATIO2,812.69×
WORKING SET / OSH → TINYLLAMA24.883 → 662.770 MB
SCOPE OF THE MEASUREMENT
The comparison measures runtime and Working Set under the stated protocol: TinyLlama was limited to one token per input. The computational tasks differ; the ratio does not measure intelligence, language quality, or equivalent task performance.
01 / PC · BENCHMARK 302 / FOLLOW THE MIGRATION TO ESP32-S3 ↗
02 / MIGRATION AND EVIDENCE
Then OSH reached the ESP32-S3.
The preceding benchmark measured OSH on a PC. This stage tests a different claim: the causal path running on two physical microcontrollers and acting on a real circuit. Explore the results and their limits.
FROM HOST TO ESP32-S3
The migration was tested along the causal path.
After Benchmark 3 on the PC, the OSH causal path ran natively on two physical ESP32-S3 units. State, trajectory, HAL candidates, selected edge, and meaning were compared: 150/150 checks. The path then drove PWM and received analog feedback for 100,000 cycles.
PC · BENCHMARK 3TWO ESP32-S3 UNITSCIRCUIT · 100,000 CYCLES
This is physical execution of the validated ESP32-S3 path; compilation for other MCU families is presented separately.
HOST / PC → ESP32-S3 → REAL CIRCUIT150/150PARITY AT FIVE LEVELSDownload technical paper ↓View paper ↗
ESP32-S3 / FINAL EXPERIMENT
The system interacted with a real circuit.
B25K reference → ADC GPIO3 → OSH → PWM GPIO14 → external 1 kΩ / 100 µF network → ADC GPIO2. The policy exercised all three observable actions.
100,000PHYSICAL CYCLES
29.525 µsINTERNAL PATH MEAN
0 / 0ADC / STATE FAILURES
INC 5,160 · HOLD 93,358 · DEC 1,482. PHYSICAL_100K_GATE and FINAL_LATCH: PASS. An oscilloscope image preserves a representative 23.0 µs path pulse; this is a separate measurement method and does not replace the internal mean.
STEP19 / TWO PHYSICAL UNITS
Causality was compared, not just output.
Thirty cases were examined at each of five boundaries: C/P/X/T/H state, trajectory and vortex, HAL candidates, selected edge ID, and meaning.
150/150CAUSAL CHECKS
5INDEPENDENT LEVELS
2PHYSICAL ESP32-S3 UNITS
The tested path preserved intermediate identity. This does not establish general reasoning or speech quality.
Open technical paper ↗SCOPE / INTERPRETATION
Separate steps, separate claims.
The compact C substrate compiled for ARM Cortex-M, RISC-V, AVR, and MIPS32. Documented physical execution is on ESP32-S3. Speech and acquisition validation took place on the host.
Clang 17FREESTANDING / -Oz
ESP32-S3PHYSICAL SILICON TESTED
Wi-FiNO PHYSICAL TEST IN THIS DOSSIER
Compilation for other targets does not establish timing, power use, peripheral behavior, or integration of a complete stack on those boards. The paper makes no claim of consciousness, biological life, or general superiority over LLMs.
Explore targets ↗03 / ARCHITECTURE
Inside the causal path.
Select a stage to see its role and the evidence boundary that supports it. State persists; each input affects a trajectory rather than an isolated response.
STAGE 01 / INPUT
Perturbation
A signal from the environment or system perturbs persistent state. In the physical experiment, an analog reference enters through GPIO3 and feedback returns through GPIO2.
EVIDENCE: ADC → OSH → PWM/RC → ADC LOOP
The parity test compares five causal levels, including the identity of the selected edge. Internal equations, coefficients, and geometry remain protected.
04 / PORTABILITY
Compact C code, four compilation families.
The compact C substrate compiled for ARM Cortex-M, RISC-V, AVR, and MIPS32 profiles. Filter the table by family. This establishes compilation portability; these boards have not undergone the physical test documented for ESP32-S3.
| Family | Profile | .text | Evidence |
|---|---|---|---|
| ARM | Cortex-M0 | 952 B | COMPILES |
| ARM | Cortex-M3 | 1,018 B | COMPILES |
| ARM | Cortex-M4 | 820 B | COMPILES |
| ARM | Cortex-M7 | 752 B | COMPILES |
| ARM | Cortex-M33 | 764 B | COMPILES |
| RISC-V | RV32IM | 1,728 B | COMPILES |
| RISC-V | RV32IMF | 960 B | COMPILES |
| RISC-V | RV32IMC / IMAC | 1,310 B | COMPILES |
| AVR | ATmega328P | 2,108 B | COMPILES |
| MIPS32 | MIPS32R2 | 1,192 B | COMPILES |
Clang 17 test, freestanding mode, -Oz. ESP32-C3/C6 appears as a RISC-V architectural proxy. ARM, RISC-V, AVR, and MIPS32 have compilation evidence, not physical tests on their boards. Documented physical execution here is on ESP32-S3.
05 / BUSINESS MODEL
What can be built around OSH.
OSH is the underlying architecture. Developer tools, manufacturer modules, and products for different sectors could be built around it. The ESP32-S3 path is a starting point for evidence; each new market requires its own validation.
One architecture. Many ways to integrate it.
The same principle could reach a manufacturer as a component, an integrator as a runtime, or an end product as an on-device capability.
COMMERCIAL HYPOTHESIS / SUBJECT TO PILOTS
01 / FOUNDATIONProtected OSH core
02 / TOOLINGRuntime · API · SDK
03 / INTEGRATIONReference designs · OEM
04 / MARKETProducts and partnerships
What could be built around it
Controlled interfaces, instrumentation, and profiles let engineering teams evaluate OSH without exposing the core.
Reference designs and adaptations for sensors, actuators, and different microcontroller families.
Robotics, automation, mobility, and IoT: concrete products built on a common mechanism.
Paid pilots with a target device, metrics, acceptance criteria, and possible follow-on integration work.
Chip, board, and equipment makers could explore packages and tools for their ecosystems.
TODAY: CORE AND ESP32-S3 EVIDENCE · NEXT: PRODUCTS AND PARTNERSHIPS TO VALIDATE
06 / VISUAL RECORD
External instrumentation, in view.
Photographs preserved in the physical validation paper. Open each image for a closer look.
These captures document different measurements. They must not be added together or directly compared with the PC benchmark median.
07 / SOURCES
Full reports from the repository.
The ESP32-S3 paper and Benchmark 3 report download from the same repository. The portability report is embedded in this HTML.
Physical Validation of an Autonomous Homeostatic Cognitive Architecture
17 pages · physical silicon, parity, endurance, oscilloscope, and analog loop.
Download paper ↗Architectural Runtime Benchmark 3
17 pages · CPU-only protocol, latency, Working Set, repetition, and interpretation.
Download Benchmark 3 ↗Multi-Microcontroller Portability Benchmark
Cross-compilation of the C substrate, ISA families, .text sizes, and limitations.
Download report ↗08 / APPLICATIONS
Close to the physical world.
The experiment opens possibilities for local integration. Each application needs its own pilot, target hardware, and acceptance criteria.
Stateful machines
Explore local decisions alongside sensors and actuators, with continuity across cycles.
Private edge
Test resident paths in equipment where latency, autonomy, and local access matter.
Autonomous systems
Investigate regulation and selection close to physical signals and timing constraints.
MCUs and devices
Measure the substrate and full integration on a specific target before making product claims.
STATUS: PROPOSED APPLICATION AREAS · NOT VALIDATED END PRODUCTS
09 / CONTACT
Let’s discuss a concrete application.
Tell us which machine, process, or product you want to explore. An initial conversation can define the target hardware, what to measure, and how to protect the integration.
OSH GLOBAL SYSTEMS, INC.
From physical proof to a measurable pilot.
- 01Use case and target hardware.
- 02Latency, memory, power, and stability.
- 03Causal parity and integration limits.
- 04Technical and commercial decision.